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Requirements

• Python
  

• LT Spice
  

• Xilinx ISE
  

• Microwind
  

Make sure to install the following packges:

pip install jupyterlab notebook matplotlib numpy opencv-python opencv-python-headless

DTSP

• Experiment 2 - Implementation & Verification of Linear Convolution

• Experiment 3A & 3B - Implement Circular Convolution

• Experiment 4 - Discrete Fourier Transform

• Experiment 5 - DFT Properties

  • Experiment 5A - Circular Convolution - DFT Properties
    
  • Experiment 5B - Circular Timeshift - DFT Properties
    
  • Experiment 5C - Linearity - DFT Properties
    
  • Experiment 5D - Parsavel - DFT Properties

• Experiment 6 - Determine Spectrum of a known siganl using DFT

• Experiment 7 - Design a digital FIR LPF
  

  • Experiment 7A - Blackman
    
  • Experiment 7B - Hamming
    
  • Experiment 7C - Hanning
    
  • Experiment 7D - Rectangular
    

• Experiment 8 - Design a digital FIR using Rectangular Window
  

  • Experiment 8A - Low Pass Filter
    
  • Experiment 8B - High Pass Filter
    
  • Experiment 8C - Band Pass Filter
    
  • Experiment 8D - Band Reject Filter
    

• Experiment 9   - IIR Butterworth Filter using BLT

• Experiment 10 - IIR Butterworth Filter using ChebyShev

DC

• Experiment 1 - Implementation of Information Theory Concepts

• Experiment 2 - Linear Block Codes

• Experiment 3 - Cyclic Codes

• Experiment 4 - Convolution Codes

• Experiment 5 - Implementation of Cyclic Redundancy Check codes

• Experiment 6 - Implementation of Line Coding Techniques

• Experiment 7 - Implementation of Digital Modulation Techniques

• Experiment 8 - Implementation of Quadrature Phase Shift Keying

DVLSI

There are both txt and main cir file.

• Experiment 1 - Output and Transfer Characteristics of NMOS and PMOS Transistor

• Experiment 2 - Transfer Characteristic of CMOS Inverter

• Experiment 3 - Transient Analysis of CMOS Inverter

• Experiment 4 - Draw CMOS inverter

• Experiment 5 - Design of 2-input NOR and NAND gate using static CMOS style

• Experiment 6 - Draw a layout of 6T SRAM cell

• Experiment 7 - 1- Bit Full Adder in Verilog HDL using data flow

• Experiment 8 - Design 8:1 Multiplexer using structural and behavioral model