VHDL-Project1

It is a BCD to 7-segment decoder using NAND gates.

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
README.md		README.md
a_block.sch		a_block.sch
a_block.sym		a_block.sym
a_test.vhd		a_test.vhd
b_block.sch		b_block.sch
b_block.sym		b_block.sym
b_test.vhd		b_test.vhd
bcdto7segment.sch		bcdto7segment.sch
c_block.sch		c_block.sch
c_block.sym		c_block.sym
c_test.vhd		c_test.vhd
d_block.sch		d_block.sch
d_block.sym		d_block.sym
d_test.vhd		d_test.vhd
e_block.sch		e_block.sch
e_block.sym		e_block.sym
e_test.vhd		e_test.vhd
f_block.sch		f_block.sch
f_block.sym		f_block.sym
f_test.vhd		f_test.vhd
finaltest.vhd		finaltest.vhd
firstproject.xise		firstproject.xise
g_block.sch		g_block.sch
g_block.sym		g_block.sym
g_test.vhd		g_test.vhd

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