ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
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Updated
Aug 29, 2018 - VHDL
ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
An implementation of an FIR half-band filter, from MATLAB floating point to SystemVerilog fixed point
Ziel dieser Übung ist ein bandbegrenztes Audiosignal in Matlab zu erzeugen und dies auf einem frequenzmodulierten Trägersignal umzuformen und in wave-Form abzuspeichern. Als nächstes wird in einem zweiten Skript in Matlab das bereits modulierten Signal eingelesen und dabei eine Frequenzdemodulation vorgenommen, um dadurch den ursprünglichen Audi…
Use this library to compute Finite Impulse Response filter.
Thesis: Custom Filter Designs on the Red Pitaya
Port of the X-CUBE-DSPDEMO on the STM32F407VET6 "blackboard"
Digital Signal Processing Hardware Lecture (eem478) Final Project
Just a random compilation of some VHDL code
Example setups for CamillaDSP filter configurations and sample convolver coefficients files.
chat webapp using which we can communicate with other person just like whatsapp.
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