Bingo game with score
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Updated
Jul 8, 2024 - JavaScript
Bingo game with score
Digital Circuits made with VHDL
Posit Arithmetic Cores generated with FloPoCo
IRIOdashboard — An analytical dashboard for IRIO (Inter-Regional Input Output) table
Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.
Free WordPress Plugin: LCM calculator to find the LCM of two or more numbers. Shows solutions by prime factorization, common multiples, cake/ladder, GCF, division, and Venn diagram. www.calculator.io/lcm-calculator/
🔁 Form multiplier & replicator for Nette Framework
Welcome to the Maths Speed Multiplier website! Our aim is to provide a welcoming and respectful environment for all participants to practice math in a fun and supportive setting.
CNF Generator for Factoring Problems
Code and data for the paper "A Theory of Countercyclical Government Multiplier"
Code and data for the paper "Optimal Public Expenditure with Inefficient Unemployment"
An 8-bit calculator that can multiply, add and subtract. Created and simulated in Quartus Prime and physically implemented in DEC-SOC1 FPGA.
N-bit Multiplier implementation in VHDL
Design and Analysis of an FPGA-based Wallace Multiplier.
Create fast and efficient standard cell based adders, multipliers and multiply-adders.
My VHDL Codes during EE214 (Digital Lab) Spring 2020-21
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