This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
systemverilog
hardware-designs
verilator
axi4-lite
axi4-protocol
vivado-simulator
axi4-lite-interface
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Updated
May 4, 2024 - SystemVerilog