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This project simulates the process of demand paging in a virtual memory system, including the use of a Translation Lookaside Buffer (TLB) to speed up memory access. The TLB is a small, fast cache that stores recent mappings of virtual memory addresses to physical memory addresses.
This is an extension of Nachos to support multiprogramming using system calls such as Exec, Exit, Read and Write to have processes request services from the kernel. Then it is further extended by a Virtual Memory Manager supported by Demand Paging and Page Replacement procedures.